publication venue for
- Reliability evaluation of FPGA based pruned neural networks. 130:1-11. 2022
- Single Event Transient Tolerant Count Min Sketches. 129:114486. 2021
- Error sensitivity study of FFT architectures implemented in FPGA. 126:1-5. 2021
- Reduced length redundancy adaptive protection for the cascaded integrator-comb interpolation filter on FPGA. 118:1-6. 2021
- Extended symbol correction algorithm for group testing based non-binary error correction codes of minimum distance dq. 113:1-5. 2020
- Reducing false positives due to double adjacent errors in instruction TLBs. 102:1-6. 2019
- Analysis of neutron sensitivity and data-flow error detection in ARM microprocessors using NEON SIMD extensions. 100-101:113346. 2019
- Dual-Core Lockstep enhanced with redundant multithread support and control-flow error detection. 100-101:113447. 2019
- Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes. 97:31-37. 2019
- Early SEU sensitivity assessment for collaborative hardening techniques: A case study of OPTOS processing architecture. 95:36-47. 2019
- Reliability of 3D Memories Using Orthogonal Latin Square codes. 95:74-80. 2019
- PTM-based hybrid error-detection architecture for ARM microprocessors. 88-90:925-930. 2018
- SEU and SEFI Error Detection and Correction on a DDR3 Memory System. 91, 1:23-30. 2018
- Modular Fault Tolerant Processor Architecture on a SoC for Space. 83:84-90. 2018