Error sensitivity study of FFT architectures implemented in FPGA Articles uri icon

publication date

  • November 2021

start page

  • 1

end page

  • 5


  • 114298


  • 126

International Standard Serial Number (ISSN)

  • 0026-2714

Electronic International Standard Serial Number (EISSN)

  • 1872-941X


  • This work studies the impact that the architectural choices can have in the error mitigation of a digital processing module such as the Fast Fourier Transform. To this purpose, several serial and pipelined architectures were implemented in FPGA using Block Triple Modular Redundancy and analysed under a fault injection approach that was previously validated with radiation. These architectures were compared with respect to error rate, common mode failure rate and signal-to-noise ratio. Experimental results show that the error rate is strongly correlated with the use of resources when using a similar architecture. However, pipelined architectures tend to have more common mode failures but with lower signal-to-noise ratio than a serial architecture.


  • Electronics


  • triple modular redundancy; fast fourier transform; sram-based fpga; common mode failures