Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes Articles uri icon

publication date

  • June 2019

start page

  • 31

end page

  • 37

volume

  • 97

International Standard Serial Number (ISSN)

  • 0026-2714

abstract

  • In recent years, there has been a growing interest in codes that can correct adjacent bit errors in memories. This is due to the increasing percentage of radiation induced errors that affect multiple cells due to technology scaling. The cells affected by the errors are physically close and in many cases adjacent. This means that in the absence of interleaving, adjacent bits will be likely to be affected by an error. A number of Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to deal with those errors. These codes have a low overhead in terms of number of additional parity check bits compared to Double Error Correction (DEC) codes. A problem is that they can introduce a significant penalty in terms of delay compared to a Single Error Correction (SEC) or a Single Error Correction and Double Error Detection (SEC-DED) code. This is due to the more complex decoding that needs to check approximately twice the number of syndrome patterns. In this paper, low delay SEC-DAEC codes are presented and the parity check matrices for 16, 32 and 64 bit data words are provided. To reduce the delay, a number of techniques are used in the construction of the code and in the implementation of the decoder. The evaluation shows that this results in significant savings compared to existing SEC-DAEC codes. Therefore, the proposed codes can be useful for high speed designs on which adjacent error correction is required.

keywords

  • error correction codes; memories; sec-ded; sec-daec; sram