PTM-based hybrid error-detection architecture for ARM microprocessors Articles uri icon

publication date

  • September 2018

start page

  • 925

end page

  • 930

volume

  • 88-90

International Standard Serial Number (ISSN)

  • 0026-2714

abstract

  • This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.

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