Analysis of SET effects in a PIC microprocessor for selective hardening Articles uri icon

publication date

  • June 2011

start page

  • 1078

end page

  • 1085


  • 3


  • 58

International Standard Serial Number (ISSN)

  • 0018-9499

Electronic International Standard Serial Number (EISSN)

  • 1558-1578


  • In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.