SET Emulation Considering Electrical Masking Effects Articles uri icon

publication date

  • August 2009

start page

  • 2015

end page

  • 2021

issue

  • 4

volume

  • 56

international standard serial number (ISSN)

  • 0018-9499

electronic international standard serial number (EISSN)

  • 1558-1578

abstract

  • A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation.Avoltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an accuracy close to analog simulation.