SET Emulation under a Quantized Delay Model Articles uri icon

publication date

  • February 2009

start page

  • 107

end page

  • 116

issue

  • 1

volume

  • 25

international standard serial number (ISSN)

  • 0923-8174

electronic international standard serial number (EISSN)

  • 1573-0727

abstract

  • Single event transient (SET) fault analysis is usually performed through digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an approach to build an FPGA based SET emulator, which implements a quantized delay model of the circuit under evaluation. Experimental results demonstrate that the quantized delay model produces accurate results and can be easily captured in an FPGA. The proposed approach can be automated to increase SET fault analysis performance by three orders of magnitude with respect to simulation.