Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures Articles uri icon

publication date

  • March 2011

start page

  • 308

end page

  • 314

issue

  • 2

volume

  • 8

international standard serial number (ISSN)

  • 1545-5971

electronic international standard serial number (EISSN)

  • 1941-0018

abstract

  • In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

keywords

  • cots microprocessors; fault injection; fault tolerance; soft errors; single event upset