Electronic International Standard Serial Number (EISSN)
1558-1578
abstract
Reduced precision redundancy (RPR) is an alternative to triple modular redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multistage circuits and analyze the error mitigation tradeoffs. As a case study, several fast Fourier transform designs were tested with low-energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach.
Classification
subjects
Electronics
keywords
fast fourier transform; fft; field programmable gate array; fpga; reduced precision redundancy; rpr; triple modular redundancy; tmr