A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA Articles uri icon

publication date

  • January 2017

start page

  • 374

end page

  • 381

issue

  • 1

volume

  • 64

international standard serial number (ISSN)

  • 0018-9499

electronic international standard serial number (EISSN)

  • 1558-1578

abstract

  • In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.

keywords

  • fault tolerance; hybrid fault-tolerance techniques; microprocessors; neutron cross-section; sees; soft errors; error-detection; microprocessors; design; mitigation