A hybrid fault-tolerant LEON3 soft core processor implemented in low-end SRAM FPGA

In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.

fault tolerance; hybrid fault-tolerance techniques; microprocessors; neutron cross-section; sees; soft errors; error-detection; microprocessors; design; mitigation

A hybrid fault-tolerant LEON3 soft core processor implemented in low-end SRAM FPGA Articles