Partial TMR in FPGAs Using Approximate Logic Circuits Articles uri icon

publication date

  • August 2016

start page

  • 2233

end page

  • 2240

issue

  • 4

volume

  • 63

international standard serial number (ISSN)

  • 0018-9499

electronic international standard serial number (EISSN)

  • 1558-1578

abstract

  • TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a fine granularity, and can provide a flexible balance between reliability and overheads. The proposed approach has been validated by the results of fault injection experiments and proton irradiation campaigns.

keywords

  • Approximate circuit
    FPGA
    Selective mitigation
    Single event upset
    Triple modular redundancy
    SEU
    Mitigation
    Design