A co-design approach for SET mitigation in embedded systems Articles uri icon

publication date

  • August 2012

start page

  • 1034

end page

  • 1039

issue

  • 4

volume

  • 59

international standard serial number (ISSN)

  • 0018-9499

electronic international standard serial number (EISSN)

  • 1558-1578

abstract

  • We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with respect to SET effects. The advantages of the proposed approach are demonstrated by means of a case study.