Electronic International Standard Serial Number (EISSN)
This paper presents a methodology to reduce the impact of double faults in a circuit by constraining the placement of its standard cells. A fault-injection emulation platform is used to analyze the single-event-induced charge sharing effect in every pair of nodes. Based on the sensitivity of each pair, guidelines are set in a commercial standard cell placement by using constraints. Results show that by correctly choosing the nodes location, the error rate resulting from double faults can be reduced compared to single fault.