Hybrid Lockstep Technique for Soft Error Mitigation Articles uri icon

publication date

  • July 2022

start page

  • 1574

end page

  • 1581


  • 7


  • 69

International Standard Serial Number (ISSN)

  • 0018-9499

Electronic International Standard Serial Number (EISSN)

  • 1558-1578


  • This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dual-core ARM microprocessor and validated with low-energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross section of the benchmarks tested, even considering the worst case scenario.


  • Electronics


  • dual cores; fault tolerance; lockstep; multithreading; proton irradiation; soft errors