REPARA: Reengineering and Enabling Performance And poweR of Applications Projects uri icon


  • European Research Project


  • GA-609666

date/time interval

  • September 1, 2013 - August 31, 2016


  • In recent years, traditional processors have not been able to translate the advances of silicon fabrication technology into
    corresponding performance gains. This has been due to weaknesses inherent in the current sequential programming model,
    which has not changed significantly since the late 1940’s, as well as due to physical constraints, such as practical limits on
    the energy consumption and the associated cooling efforts for a processor. To keep satisfying the ever-growing demand for
    computing power, these difficulties have forced a shift from homogeneous machines relying on a one single kind of fast
    processing element (the CPU) such as typical PCs some years ago, programmed mostly sequentially, to heterogeneous
    architectures combining different kinds of processors (such as CPUs, GPUs and DSPs) each specialized for certain tasks,
    and programmed in a highly parallel fashion yet poorly optimising the available resources towards performance and low
    energy consumption.
    The REPARA project joins forces of experts in software engineering methodology, development tools, computer hardware
    design and analysis, all working hand-in-hand with industrial end-users to achieve a unified programming model for
    heterogeneous computers developing also the required automated software support tools. Relative to the base line of a
    sequential algorithm executed on a current general-purpose processor, REPARA expects to achieve at least a 50% reduction
    of energy consumption combined with a performance improvement of at least by a factor of two. REPARA will also allow
    for an increased productivity realizing designs in half of the development time that would be required using non-unified
    programming methods for the different components of a heterogeneous system. Combined, REPARA will lead to fourfold gain
    in efficiency for energy savings and performance. These objectives will be verified in 5 real-world use cases in the domains of
    railway, healthcare and industrial ma


  • parallel heterogeneous computing; energy-efficiency; performance; maintainability; parallelisation; software refactoring; reconfigurable hardware; runtime engines