Low delay non-binary error correction codes based on Orthogonal Latin Squares

Due to the scaling of technology and the environment effects, such as radiation, memory systems that are on board of spacecraft such as satellites, are more sensitive to errors. This kind of error is difficult to predict and its correction in real-time is crucial for the correct behavior of the whole system. In this paper, a low delay fully parallel non-binary decoder based on orthogonal Latin squares defined in a Galois field is presented. The proposed approach corrects a single symbol in GF(2q) with very low complexity applying a one-step majority logic algorithm that allows reaching high-speed decoding with very low latency. The decoder introduced in this manuscript was implemented for 64 and 128-bit codes over GF(28) in a 45 nm CMOS process. Our implementation outperforms state-of-the-art decoders with the same error correction capacity, achieving lower latency, delay and area in both cases. The results show that the proposed solution can be suitable for the protection of some types of memories like DRAM or 3D-memories and other radioactive environment applications.

Low delay non-binary error correction codes based on Orthogonal Latin Squares Articles