Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase

Memory systems increase their demand for error correction capacity moving from single and double error correction decoders to triple and quadruple ones (TEC and QEC). New proposals for TEC and QEC decoders take advantage of some classic algorithms that were discarded when more efficient options appear. However, these algorithms can be applied to softdecoding architectures with a negligible increase in complexity. This brief proposes a new method to select the test vector to be decoded in a soft-decision low-complexity Chase algorithm, without requiring the computation of 2 η polynomials of location or 2 η searches of roots. The decodable test vector is pre-selected just with the syndrome information and with a very small percentage of hardware resources compared to hard-decision TEC and QEC. Compared to hard-decision, the proposed decoder obtains a coding gain between 0.4 and 0.8dB, depending on the codeword length and the order of the Galois Field, at a cost of 6.5% of extra area in the worst case. This solution introduces a performance loss of 0.1dB compared to the traditional low-complexity Chase algorithm.

Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase Articles