A survey of techniques for reducing interference in real-time applications on multicore platforms Articles uri icon

publication date

  • February 2022

start page

  • 21853

end page

  • 21882


  • 10

Electronic International Standard Serial Number (EISSN)

  • 2169-3536


  • This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.


  • Computer Science


  • real-time systems; architecture; multicore; timing analysis; schedulability analysis; wcet; co-runner interference