Reduced resolution redundancy: A novel approximate error mitigation technique Articles uri icon

publication date

  • February 2022

start page

  • 20643

end page

  • 20651

volume

  • 10

International Standard Serial Number (ISSN)

  • 2169-3536

Electronic International Standard Serial Number (EISSN)

  • 2169-3536

abstract

  • Error mitigation techniques, such as Triple Modular Redundancy, introduce very large overheads. To alleviate this overhead, approximate techniques can be used. In this work we propose a novel approximate error mitigation technique based on using redundant circuits with lower resolution. As a representative case study, the approach is demonstrated for a Fast Fourier Transform, for which an optimized architecture is proposed. The approach is validated through fault injection. Experimental results show that Reduced Resolution Redundancy can significantly reduce the overhead and achieve an excellent error mitigation performance and a low sensitivity to uncorrectable errors.

subjects

  • Computer Science
  • Electronics
  • Mechanical Engineering
  • Nuclear Energy
  • Telecommunications

keywords

  • fault tolerance; triple modular redundancy; fast fourier transform; fpga; approximate computing