A Pulse Frequency Modulation VCO-ADC in 40nm Articles uri icon


publication date

  • January 2019

start page

  • 51

end page

  • 55


  • 1


  • 66


  • This brief describes the architecture and implementation of a novel voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC). Instead of a ring oscillator, the VCO is built with a pulse frequency modulation architecture where an analog feedback loop ensures both oscillation and linearity of the voltage-to-frequency conversion. A multibit first-order noise-shaped output is achieved by sampling a digital delay line that acts as a part of the oscillator and as a multibit quantizer. A prototype has been implemented in a 40-nm CMOS process. Although most of the circuit elements are taken from a standard digital library, a transconductor is required as the input stage. To ensure proper linearity, a bulk-driven transconductor has been designed. The ADC measurements reach 53 dB of SNDR at 1 GHz sampling frequency in a 20-MHz bandwidth with a pseudo-differential architecture. Powered at 1.1 V, the power consumption is 3.5 mW. The active area is 0.08 mm 2 . The resulting figure-of-merit equals 242 fJ/step.


  • Electronics


  • analog-to-digital conversion; noise shaping; pulse frequency modulation; voltage controlled oscillator