Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection Articles uri icon

authors

  • Gonz├ílez Toral, Ricardo
  • LIU, SHANSHAN
  • REVIRIEGO VASALLO, PEDRO
  • MAESTRO, JUAN ANTONIO

publication date

  • April 2018

start page

  • 1293

end page

  • 1302

issue

  • 4

volume

  • 65

International Standard Serial Number (ISSN)

  • 1549-8328

Electronic International Standard Serial Number (EISSN)

  • 1558-0806

abstract

  • Soft errors produced by radiation events can cause malfunctions in modern day electronics. To preserve the system functionality, its elements must be protected against the effects of these events. Two of the possible techniques usually employed to implement fault tolerant registers are triple modular redundancy (TMR) and single error correcting (SEC) codes. However, the use of these techniques increases circuit area, timing, and power consumption to different extents. In this paper, we study the influence of each of these approaches on the circuit when they are implemented in application-specific integrated circuits and, based on the results, present some guidelines to choose between both of them depending on the design requirements. Additionally, we present a new low power fault tolerant technique destined for registers in which a subset of bits have a lower switching activity than the rest. This approach is based on the idea of combining TMR and SEC codes within a register to implement a hybrid protection that can exploit the strengths of each of the techniques. Our results show that the use of this technique achieves both power and area savings with respect to TMR in most cases, whereas it achieves large power savings with respect to SEC codes at the cost of increasing the area overhead.

keywords

  • fault tolerance; error correction codes; power dissipation; redundancy; linear codes