A lightweight implementation of the Tav-128 hash function Articles uri icon

publication date

  • June 2017

issue

  • 11

volume

  • 14

international standard serial number (ISSN)

  • 1349-2543

electronic international standard serial number (EISSN)

  • 1349-9467

abstract

  • In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria: area, throughput, and a trade-off between both of them.

keywords

  • hardware implementation; hash function; ASIC; FPGA