Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches Articles uri icon

publication date

  • December 2016

start page

  • 1871

end page

  • 1883

issue

  • 4

volume

  • 65

international standard serial number (ISSN)

  • 0018-9529

electronic international standard serial number (EISSN)

  • 1558-1721

abstract

  • Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.

keywords

  • Approximate logic circuit
    Error mitigation
    Evolutionary computing
    Single-event transient (set)
    Single-event upset (seu)
    Combinational-circuits
    Fault-tolerance
    Masking
    Redundancy
    Simulation