A comparative study of an X-Ray Tomography Reconstruction Algorithm in Accelerated and Cloud Computing Systems Articles uri icon

publication date

  • December 2015

start page

  • 5538

end page

  • 5556


  • 18


  • 27

International Standard Serial Number (ISSN)

  • 1532-0626

Electronic International Standard Serial Number (EISSN)

  • 1532-0634


  • With the increase of resolution in medical image scanners and the need of faster reconstruction methods, new ways of exploiting the inherent parallelism of reconstruction algorithms have arisen. In this paper, we present Mangoose++, an application to perform X-ray computed tomography that supports multiple grades of parallelism. This parallelism is tackled with two different approaches: the usage of parallel nodes with multicore CPUs in a cloud environment and the usage of high-performance computing (HPC)-based parallel architectures such as general-purpose computing on graphics processing unit (GPGPU) or Intel Xeon Phi. In this paper, we show the design and implementation of the application in three types of platforms related to the previous mentioned approaches, comparing and analyzing the performance, resource utilization, and scalability of each platform. Accelerators offer high performance for data sizes that fit inside the accelerator memory. This is the main advantage of Intel Xeon Phi that, in this work, obtains similar performance results than compute unified device architecture (CUDA)-based GPGPU versions, comparing with cards with less memory capacity. In our evaluation experiments, we additionally analyze and discuss the costs and efficiency of Mangoose++ over Amazon Compute Cloud platform, demonstrating that lower times can be achieved in a reasonable price compared with owned HPC-based hardware. A comparison between distinct hardware configurations is provided for emphasizing on the advantages and disadvantages of each one. Copyright (C) 2015 John Wiley & Sons, Ltd.


  • cloud computing; accelerators; computed tomography; gpgpu; intel xeon phi; implementation; parallel; hardware