authors
- PUN GARCIA, ERNESTO
- PREFASI SEN, ENRIQUE JOSE
- PATON ALVAREZ, SUSANA
- HERNANDEZ CORPORALES, LUIS
Continuous Time Sigma-Delta Modulator Based on Binary Weighted Charge Balance
Articles
Overview
published in
- ELECTRONICS LETTERS Journal
publication date
- April 2009
start page
- 458
end page
- 460
issue
- 9
volume
- 45
Digital Object Identifier (DOI)
International Standard Serial Number (ISSN)
- 0013-5194
Electronic International Standard Serial Number (EISSN)
- 1350-911X
abstract
- A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.