electronic international standard serial number (EISSN)
Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators.