Projects Granted
- Architecture design of 50/100 MHz MASH PWM-ADC
- Circuit level design of 50/100 MHz MASH PWM-ADC
- Exploration of High Bandwidth Data Converters based on Time Encoded Architectures
- High Bandwidth Data Converters based on Time Encoded Architectures (HBDCTEA)
- Oversampled Data Converters for Home Networking (ODCHN)
- Research and Development Agreement between Universidad Carlos III de Madrid and Infineon Technologies Austria AG