Electronic International Standard Serial Number (EISSN)
Non volatile memory (NVM) technologies are being explored extensively to replace conventional SRAM based memories. The main focus of this paper is the exploration of a NVM based instruction memory in low power embedded systems for wireless or multimedia target applications. A SRAM based traditional instruction memory organization suitable for the target applications is taken as the base. Different Resistive RAM (ReRAM) based organizations are then designed as alternatives keeping in mind their limitations (write process related), and energy and performance trade-offs. The NVM array design is explored and optimized based on energy and performance trade-offs. Dynamic instruction mapping and architectural design changes are utilized to minimize ReRAM limitations and maximize its positive contributions. Energy and performance values are obtained by extension of CACTI models, Spice and VHDL simulations. The best ReRAM based hybrid instruction memory organization that utilizes our proposed methodology showed significantly lower energy consumption (up-to 82.07% read energy reduction) even in case of 0% performance penalty.
instruction memory organization; loop buffer; non volatile memory; very wide register