Modern satellite communication systems require on-board processing (OBP) for performance improvements, and SRAM-FPGAs are an attractive option for OBP implementation. However, SRAM-FPGAs are sensitive to radiation effects, among which single event upsets (SEUs) are important as they can lead to data corruption and system failure. This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory. Analysis and fault injection experiments are conducted to verify that over 97% of the SEUs on user memory would not lead to output errors. To achieve a better reliability, selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead. Although the results are obtained for a specific FPGA implementation, the developed reliability estimation model and the general conclusions still hold for other implementations.
fault tolerance; fpga; on-board processing; single event upsets; user memory; viterbi decoder