Multiple Cell Upsets Inside Aircrafts. New Fault-Tolerant Architecture Articles uri icon

publication date

  • February 2019

start page

  • 332

end page

  • 342

issue

  • 1

volume

  • 55

international standard serial number (ISSN)

  • 0018-9251

electronic international standard serial number (EISSN)

  • 1557-9603

abstract

  • Multiple cell upsets (MCU) is an issue that has to be dealt with when designing electronics for working in a radiated environment. Furthermore, the constant evolution of ICs integration density causes an increment in the MCUs span. These issues are typical in aviation applications, where, additionally, fault-tolerant (FT) performance is required. FT systems are typically based on a redundancy concept for storing and retrieving healthy information, for example, with a triple modular redundancy (TMR) scheme. The main issue with redundancy is design oversizing. On the other hand, reconfiguration-based techniques allow error scrubbing with a limited overhead. The main drawback here is overhead vulnerability to radiation, which is invalid for FT requirements. This paper proposes a new hybrid architecture that takes advantage of the optimized performance of reconfiguration-based techniques supported on extremely compressed redundant information nonvulnerable to radiation, referred to in this paper as hardwired seed bits (HSB). It also includes different known techniques, such as interleaving, error detection and correction (EDAC) algorithms, etc., for optimizing the final architecture as much as possible. As a result, the proposed approach meets FT requirements thanks to nonvulnerable tiny redundant information combined with an optimized performance through EDAC-based implementation.

keywords

  • bit upset; error; seu; neutrons