High-level programming for heterogeneous and hierarchical parallel systems Articles uri icon

publication date

  • November 2018

start page

  • 804

end page

  • 806

issue

  • 6

volume

  • 32

International Standard Serial Number (ISSN)

  • 1094-3420

Electronic International Standard Serial Number (EISSN)

  • 1741-2846

abstract

  • High-Level Heterogeneous and Hierarchical Parallel Systems (HLPGPU) aims to bring together researchers and practitioners to present new results and ongoing work on those aspects of high-level programming relevant, or specific to general-purpose computing on graphics processing units (GPGPUs) and new architectures. The 2016 HLPGPU symposium was an event co-located with the HiPEAC conference in Prague, Czech Republic. HLPGPU is targeted at high-level parallel techniques, including programming models, libraries and languages, algorithmic skeletons, refactoring tools and techniques for parallel patterns, tools and systems to aid parallel programming, heterogeneous computing, timing analysis and statistical performance models.

keywords

  • gpgpu; heterogeneous; domain-specific parallel patterns; performance; programming models