Novel fault tolerant Multi-Bit Upset (MBU) Error-Detection and Correction (EDAC) architecture Supervised Theses uri icon

authors

  • JIMENEZ OLAZABAL, ANDRES

university

  • UNIVERSIDAD CARLOS III DE MADRID

school / faculty

  • ESCUELA POLITECNICA SUPERIOR

reading date

  • 2018

department

  • TECNOLOGIA ELECTRONICA

keywords

  • fault-tolerant systems; error-detection and correction; edac; single event upset; seu; multiple bit upset; mbu; hardwired seed bits; hsb; aeronautical industry