Novel fault tolerant Multi-Bit Upset (MBU) Error-Detection and Correction (EDAC) architecture Directed Thesis uri icon

authors

  • JIMENEZ OLAZABAL, ANDRES

university

  • UNIVERSIDAD CARLOS III DE MADRID

school / faculty

  • ESCUELA POLITECNICA SUPERIOR

reading date

  • 2018

department

  • TECNOLOGIA ELECTRONICA

keywords

  • fault-tolerant systems; error-Detection and Correction; EDAC; single event upset; SEU; multiple bit upset; MBU; hardwired seed bits; HSB; aeronautical industry